View 5962-9176402M3A_751659.PDF datasheet online --- IC-ON-LINE

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a
FEATURES +5 V to 15 V Operation Unipolar or Bipolar Operation True Voltage Output Double-Buffered Inputs Reset to Min (DAC8413) or Center Scale (DAC8412) Fast Bus Access Time Readback APPLICATIONS Automatic Test Equipment Digitally Controlled Calibration Servo Controls Process Control Equipment GENERAL DESCRIPTION
Quad, 12-Bit DAC Voltage Output with Readback DAC8412/DAC8413
FUNCTIONAL BLOCK DIAGRAM
VLOGIC DATA I/O 12 I/O PORT INPUT REG A INPUT REG B CONTROL LOGIC INPUT REG C INPUT REG D OUTPUT REG A OUTPUT REG B OUTPUT REG C OUTPUT REG D VDD VREFH DAC A VOUTA
DGND A0 A1 R/W CS
DAC B
VOUTB
DAC C
VOUTC
DAC D
VOUTD
RESET LDAC VREFL VSS
The DAC8412 and DAC8413 are quad, 12-bit voltage output DACs with readback capability. Built using a complementary BiCMOS process, these monolithic DACs offer the user very high package density. Output voltage swing is set by the two reference inputs VREFH and VREFL. By setting the VREFL input to 0 V and VREFH to a positive voltage, the DAC will provide a unipolar positive output range. A similar configuration with VREFH at 0 V and VREFL at a negative voltage will provide a unipolar negative output range. Bipolar outputs are configured by connecting both VREFH and VREFL to nonzero voltages. This method of setting output voltage range has advantages over other bipolar offsetting methods because it is not dependent on internal and external resistors with different temperature coefficients.
Digital controls allow the user to load or read back data from any DAC, load any DAC and transfer data to all DACs at one time. An active low RESET loads all DAC output registers to midscale for the DAC8412 and zero scale for the DAC8413. The DAC8412/DAC8413 are available in 28-lead plastic DIP, PLCC and LCC packages. They can be operated from a wide variety of supply and reference voltages with supplies ranging from single +5 V to 15 V, and references from +2.5 V to 10 V. Power dissipation is less than 330 mW with 15 V supplies and only 60 mW with a +5 V supply. For MIL-STD-883 applications, contact your local ADI sales office for the DAC8412/DAC8413/883 data sheet which specifies operation over the -55C to +125C temperature range. All 883 parts are also available on Standard Military Drawings 5962-91 76401MXA through 76404M3A.
0.500 0.375
LINEARITY ERROR - LSB
+125 C +25 C
0.250 0.125 0
-55 C -0.125 -0.250 -0.375 -0.500 VDD = +15V VSS = -15V VREFH = +10V VREFL = -10V TA = -55 C, +25 C, +125 C 0 512 1024 1536 2046 2548 2560 DIGITAL INPUT CODE - Decimal 3072 4096
Figure 1. INL vs. Code Over Temperature
REV. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2000
ELECTRICAL CHARACTERISTICS -40 C T +85 C unless otherwise noted. See Note 1 for supply variations.)
A
DAC8412/DAC8413-SPECIFICATIONS V, V (@ V = +15.0 V, V = -15.0
DD SS
LOGIC
= +5.0 V, VREFH = +10.0 V, VREFL = -10.0 V,
Min Typ 0.25 -1 2 2 15 20 1 VDD - 2.5 VREFH - 2.5 +2.75 +2.75 Max 0.5 1 Units LSB LSB LSB LSB LSB ppm/C ppm/C LSB V V mA mA kHz mA s V/s dB V V V V A pF nV-s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ppm/V mA mA mW
Parameter Integral Nonlinearity Error Differential Nonlinearity Error Min-Scale Error Full-Scale Error Min-Scale Tempco Full-Scale Tempco Linearity Matching REFERENCE Positive Reference Input Voltage Range Negative Reference Input Voltage Range Reference High Input Current Reference Low Input Current Large Signal Bandwidth AMPLIFIER CHARACTERISTICS Output Current Settling Time Slew Rate Analog Crosstalk LOGIC CHARACTERISTICS Logic Input High Voltage Logic Input Low Voltage Logic Output High Voltage Logic Output Low Voltage Logic Input Current Input Capacitance Digital Feedthrough3 LOGIC TIMING CHARACTERISTICS 3 Chip Select Write Pulsewidth Write Setup Write Hold Address Setup Address Hold Load Setup Load Hold Write Data Setup Write Data Hold Load Data Pulsewidth Reset Pulsewidth Chip Select Read Pulsewidth Read Data Hold Read Data Setup Data to Hi Z Chip Select to Data SUPPLY CHARACTERISTICS Power Supply Sensitivity Positive Supply Current Negative Supply Current Power Dissipation
Symbol INL INL DNL VZSE VFSE TCVZSE TCVFSE
Conditions E Grade F Grade Monotonic Over Temperature RL = 2 k RL = 2 k RL = 2 k RL = 2 k Adjacent DAC Matching Note 2 Note 2
IREFH IREFL BW IOUT tS SR
VREFL + 2.5 -10 -2.75 +1.5 0 +2 -3 dB, VREFH = 0 V to +10 V p-p 160 RL = 2 k, CL = 100 pF -5 to 0.01%, 10 V Step, RL = 1 k 10% to 90%
+5 10 2.2 72
VINH VINL VOH VOL IIN CIN
TA = +25C TA = +25C IOH = +0.4 mA IOL = -1.6 mA
2.4 0.8 2.4 0.4 1 8 5 80 0 0 0 0 70 30 20 0 170 140 130 0 0 200 160 150 12 330
VREFH = +2.5 V, VREFL = 0 V Note 4 tWCS tWS tWH tAS tAH tLS tLH tWDS tWDH tLDW tRESET tRCS tRDH tRDS tDZ tCSD PSS IDD ISS PDISS tWCS = 80 ns tWCS = 80 ns
tWCS = 80 ns tWCS = 80 ns
tRCS = 130 ns tRCS = 130 ns CL = 10 pF CL = 100 pF 14.25 V VDD 15.75 V VREFH = +2.5 V
-10
8.5 -6.5
NOTES 1 All supplies can be varied 5%, and operation is guaranteed. Device is tested with nominal supplies. 2 Operation is guaranteed over this reference range, but linearity is neither tested nor guaranteed. 3 All parameters are guaranteed by design. 4 All input control signals are specified with tr = tf = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V. Specifications subject to change without notice.
-2-
REV. D
DAC8412/DAC8413 ELECTRICAL CHARACTERISTICS
Parameter Integral Nonlinearity Error
(@ VDD = VLOGIC = +5.0 V 5%, VSS = 0.0 V, VREFH = +2.5 V, VREFL = 0.0 V, and VSS = -5.0 V 5%, VREFL = -2.5 V, -40 C TA +85 C unless otherwise noted. See Note 1 for supply variations.)
Conditions E Grade F Grade VSS = 0.0 V; E Grade2 VSS = 0.0 V; F Grade2 Monotonic Over Temperature VSS = -5.0 V VSS = -5.0 V VSS = 0.0 V VSS = 0.0 V Min Typ 1/2 Max 1 2 2 4 4 4 8 8 100 100 1 VREFL + 2.5 0 -2.5 -1.0 450 -1.25 7 2.2 2.4 0.8 2.4 0.45 1 8 Note 5 150 0 0 0 0 70 50 20 0 180 150 170 20 0 200 320 100 7 VSS = -5.0 V VSS = 0 V VSS = -5 V -10 60 110 +1.25 VDD - 2.5 VREFH - 2.5 VREFH - 2.5 +1.0 Units LSB LSB LSB LSB LSB LSB LSB LSB LSB ppm/C ppm/C LSB V V V mA kHz mA s V/s V V V V A pF ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ppm/V mA mA mW mW
Symbol INL INL INL INL DNL VZSE VFSE VZSE VFSE TCVZSE TCVFSE
Differential Nonlinearity Error Min-Scale Error Full-Scale Error Min-Scale Error Full-Scale Error Min-Scale Tempco Full-Scale Tempco Linearity Matching REFERENCE Positive Reference Input Voltage Range Negative Reference Input Voltage Range Reference High Input Current Large Signal Bandwidth AMPLIFIER CHARACTERISTICS Output Current Settling Time Slew Rate LOGIC CHARACTERISTICS Logic Input High Voltage Logic Input Low Voltage Logic Output High Voltage Logic Output Low Voltage Logic Input Current Input Capacitance LOGIC TIMING CHARACTERISTICS 4 Chip Select Write Pulsewidth Write Setup Write Hold Address Setup Address Hold Load Setup Load Hold Write Data Setup Write Data Hold Load Data Pulsewidth Reset Pulsewidth Chip Select Read Pulsewidth Read Data Hold Read Data Setup Data to Hi Z Chip Select to Data SUPPLY CHARACTERISTICS Power Supply Sensitivity Positive Supply Current Negative Supply Current Power Dissipation
-1
Adjacent DAC Matching Note 3 VSS = 0.0 V VSS = -5.0 V Code 000H -3 dB, VREFH = 0 V to 2.5 V p-p RL = 2 k, CL = 100 pF to 0.01%, 2.5 V Step, RL = 1 k 10% to 90% TA = +25C TA = +25C IOH = +0.4 mA IOL = -1.6 mA
IREFH BW IOUT tS SR VINH VINL VOH VOL IIN CIN tWCS tWS tWH tAS tAH tLS tLH tWDS tWDH tLDW tRESET tRCS tRDH tRDS tDZ tCSD PSS IDD ISS PDISS
tWCS = 150 ns tWCS = 150 ns
tWCS = 150 ns tWCS = 150 ns
tRCS = 170 ns tRCS = 170 ns CL = 10 pF CL = 100 pF
12
NOTES 1 All supplies can be varied 5%, and operation is guaranteed. Device is tested with V DD = +4.75 V. 2 For single supply operation only (V REFL = 0.0 V, VSS = 0.0 V): Due to internal offset errors, INL and DNL are measured beginning at code 2 (002 H). 3 Operation is guaranteed over this reference range, but linearity is neither tested nor guaranteed. 4 All parameters are guaranteed by design. 5 All input control signals are specified with tr = tf = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V. Specifications subject to change without notice.
REV. D
-3-
DAC8412/DAC8413
t RCS
CS
80ns
t RDS
R/W
t RDH
CS tWS tWH
t AS
A0/A1
t AH
R/W tAS
t DZ
DATA OUT HI-Z DATA VALID HI -Z
ADDRESS
ADDRESS ONE
ADDRESS TWO
ADDRESS THREE
ADDRESS FOUR tLS tLH
t CSD
Figure 2. Data Output (Read Timing)
t WCS
CS
LDAC tWDS DATA IN DATA1 VALID DATA2 VALID DATA3 VALID DATA4 VALID tLDW tWDH
t WS
R/W
t WH
Figure 5. Double Buffer Mode
VDD VREFH VREFL
t AS
A0/A1
t AH
t LS
LDAC
t LH
t LDW
D1
+ C1 D1
+ C1 C1 + D1 C2 N/C C2 N/C
R2
R2
R1
VREFH VOUTB VOUTA VSS DGND RESET LDAC
VREFL VOUTC VOUTD VDD VLOGIC CS A0 A1 R/W DB11 DB10 DB9 DB8 DB7 R5 R4 R4 * ONCE PER PORT C2 N/C N/C C2 R3 R3 R3
t WDS
DATA IN
t WDH
t RESET
RESET
Figure 3. Data WRITE (Input and Output Registers) Timing
80ns CS tWS R/W tAS ADDRESS ADDRESS ONE tLS LDAC tWDS DATA IN DATA1 VALID DATA2 VALID DATA3 VALID DATA4 VALID tWDH ADDRESS TWO ADDRESS THREE ADDRESS FOUR tLH
DGND D1 VSS + C1 R6
DB0 DB1 DB2 DB3 DB4
tWH
R1
DB5 DB6
VDD = +15V, VSS = -15V, VREFH = +10V, VREFL = 0V R1 = 10 , R2 = 100 , R3 = 5k , R4 = 10k , R5 = 100k , R6 = 47 FOR LCC, R6 = 100 FOR DIP C1 = 4.7 F (ONCE PER PORT), C2 = 0.01 F (EACH DEVICE) D1 = 1N4001 OR EQUIVALENT (ONCE PER PORT)
Figure 6. Burn-In Diagram
Figure 4. Single Buffer Mode
-4-
REV. D
DAC8412/DAC8413
ABSOLUTE MAXIMUM RATINGS Thermal Resistance
(TA = +25C unless otherwise noted) VSS to VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V, +33.0 V VSS to VLOGIC . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V, +33.0 V VLOGIC to DGND . . . . . . . . . . . . . . . . . . . . . . -0.3 V, +7.0 V VSS to VREFL . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V, +VSS-2.0 V VREFH to VDD . . . . . . . . . . . . . . . . . . . . . . . . . +2.0 V, +33.0 V VREFH to VREFL . . . . . . . . . . . . . . . . . . . . . . . . +2.0 V, VSS-VDD Current into Any Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . 15 mA Digital Input Voltage to DGND . . . . . -0.3 V, VLOGIC +0.3 V Digital Output Voltage to DGND . . . . . . . . . . -0.3 V, +7.0 V Operating Temperature Range ET, FT, EP, FP, FPC . . . . . . . . . . . . . . . . -40C to +85C AT, BT, BTC . . . . . . . . . . . . . . . . . . . . . -55C to +125C Dice Junction Temperature . . . . . . . . . . . . . . . . . . . . . +150C Storage Temperature . . . . . . . . . . . . . . . . . . -65C to +150C Power Dissipation Package . . . . . . . . . . . . . . . . . . . 1000 mW Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . +300C
Package Type
JA*
JC
Units
28-Lead Plastic DIP (P) 48 28-Lead Hermetic Leadless Chip Carrier (TC) 70 28-Lead Plastic Leaded Chip Carrier (PC) 63
22 C/W 28 C/W 25 C/W
*JA is specified for worst-case mounting conditions, i. e., JA is specified for device in socket.
ORDERING INFORMATION 1, 2
INL (LSB) 1 1.5 0.5 1 1 1.5 0.5 1
Military3 Temperature -55 C to +125 C DAC8412BTC/883
Extended Industrial3 Temperature -40 C to +85 C DAC8412FPC DAC8412EP DAC8412FP DAC8413FPC
Package Description PLCC LCC Plastic DIP Plastic DIP PLCC LCC Plastic DIP Plastic DIP
Package Option P-28A E-28A N-28 N-28 P-28A E-28A N-28 N-28
DAC8413BTC/883 DAC8413EP DAC8413FP
NOTES 1 Die Size 0.225 x 0.165 inches, 37,125 sq. mils (5.715 x 4.191 mm, 23.95 sq. mm). Substrate should be connected to V DD; Transistor Count = 2595. 2 Burn-in is available on extended industrial temperature range parts in cerdip. 3 A complete /883 data sheet is available. For availability and burn-in information, contact your local sales office.
CAUTION
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation at or above this specification is not implied. Exposure to the above maximum rating conditions for extended periods may affect device reliability. 2. Digital inputs and outputs are protected, however, permanent damage may occur on unprotected units from high-energy electrostatic fields. Keep units in conductive foam or packaging at all times until ready to use. Use proper antistatic handling procedures. 3. Remove power before inserting or removing units from their sockets. 4. Analog outputs are protected from short circuit to ground or either supply.
WARNING!
ESD SENSITIVE DEVICE
REV. D
-5-
DAC8412/DAC8413
PIN FUNCTION DESCRIPTIONS PIN CONFIGURATIONS Plastic DIP
VREFH 1 VOUTB 2 VOUTA 3 VSS 4 DGND 5 RESET 6 LDAC 7 DB0 (LSB) 8 DB1 9 DB2 10 DB3 11 DB4 12 DB5 13 DB6 14 28 VREFL 27 VOUTC 26 VOUTD 25 VDD
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Name VREFH VOUTB VOUTA VSS DGND RESET LDAC DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 R/W
Description High-Side DAC Reference Input DAC B Output DAC A Output Lower-Rail Power Supply Digital Ground Reset Input and Output Registers to all 0s, Enabled at Active Low Load Data to DAC, Enabled at Active Low Data Bit 0, LSB Data Bit 1 Data Bit 2 Data Bit 3 Data Bit 4 Data Bit 5 Data Bit 6 Data Bit 7 Data Bit 8 Data Bit 9 Data Bit 10 Data Bit 11, MSB Active Low to Write Data to DAC. Active High to Readback Previous Data at Data Bit Pins with VLOGIC Connected to +5 V Address Bit 1 Address Bit 0 Chip Select, Enabled at Active Low Voltage Supply for Readback Function. Can be Open Circuit If Not Used Upper-Rail Power Supply DAC D Output DAC C Output Low-Side DAC Reference Input
DAC8412 DAC8413
TOP VIEW (NOT TO SCALE)
24 VLOGIC 23 CS 22 A0 21 A1 20 R/W 19 DB11 (MSB) 18 DB10 17 DB9 16 DB8 15 DB7
PLCC
VOUTA VOUTB VOUTC VOUTD VREFH VREFL VSS
4 DGND RESET LDAC DB0 (LSB) DB1 5 6 7 8 9
3
2
1
28 27 26 25 VDD 24 VLOGIC
21 22 23 24 25 26 27 28
A1 A0 CS VLOGIC VDD VOUTD VOUTC VREFL
DAC8412PC DAC8413PC
23 CS 22 A0 21 A1
DB2 10 DB3 11
TOP VIEW (NOT TO SCALE)
20 R/W 19 DB11 (MSB)
12 13 14 15 16 17 18
DB10
VOUTD
DB4
DB5
DB6
DB7
DB8
VREFL
LCC
VOUTA VOUTB VOUTC VREFH VSS
4 DGND RESET LDAC DB0 (LSB) DB1 5 6 7 8 9
3
2
1
28 27 26 25 VDD 24 VLOGIC
DB9
DAC8412TC DAC8413TC
TOP VIEW (NOT TO SCALE) 12 13 14 15 16 17 18
DB4 DB5 DB6 DB7 DB8 DB9 DB10
23 CS 22 A0 21 A1 20 R/W 19 DB11 (MSB)
DB2 10 DB3 11
-6-
REV. D
Typical Performance Characteristics- DAC8412/DAC8413
MAXIMUM LINEARITY ERROR - LSB
MAXIMUM LINEARITY ERROR - LSB
+2
MAXIMUM LINEARITY ERROR - LSB
+1
VDD = +5V VSS = 0V VREFL = 0V TA = +25 C
0.3
+1 0
0
0.2 VDD = +15V VSS = -15V VREFL = 0V TA = +25 C
-1
VDD = +15V VSS = -15V VREFL = -10.0V TA = +25 C 6 7 8 9 10 VREFH - Volts 11 12
-1
0.1
-2
1
2 VREFH - Volts
3
6
8 10 VREFH - Volts
12
Figure 7. DNL vs. VREFH
Figure 8. DNL vs. VREFH
Figure 9. INL vs. VREFH
0.4
0.3 VDD = +15V VSS = -15V VREFH = +10V VREFL = -10V X+3
MAXIMUM LINEARITY ERROR - LSB
ZERO-SCALE ERROR - LSB
FULL-SCALE ERROR - LSB
+1
0.2
0.1 X -0.1 X-3 -0.3 VDD = +15V VSS = -15V VREFH = +10V VREFL = -10V 0 200 400 600 800 1000 T = HOURS OF OPERATION AT +125 C
0 X+3 -0.2 X -0.4 X-3 -0.6 0
0
-1
VDD = +5V VSS = 0V VREFL = 0V TA = +25 C 1 2 VREFH - Volts 3
-0.5
-0.7 1000 200 400 600 800 T = HOURS OF OPERATION AT +125 C
Figure 10. INL vs. VREFH
Figure 11. Full-Scale Error vs. Time Accelerated by Burn-In
0.3
Figure 12. Zero-Scale Error vs. Time Accelerated by Burn-In
0.2 VDD = +15V VSS = -15V VREFH = +10V VREFL = -10V
FULL-SCALE ERROR - LSB
ZERO-SCALE ERROR - LSB
0
0.1
VDD = +15V VSS = -15V VREFH = +10V VREFL = -10V DAC A
-0.2
DAC A
-0.1 DAC D
DAC C
DAC D DAC B
-0.4 DAC C
-0.3
DAC B
-0.6 -75
0 75 TEMPERATURE - C
150
-0.5 -75
0 75 TEMPERATURE - C
150
Figure 13. Full-Scale Error vs. Temperature
Figure 14. Zero-Scale Error vs. Temperature
REV. D
-7-
DAC8412/DAC8413
0.37500 0.26125
LINEARITY ERROR - LSB
LINEARITY ERROR - LSB
0.500 0.375 0.250 0.125 0 -0.125 -0.250 -0.375 -0.500 VDD = +15V VSS = -15V VREFH = +10V VREFL = -10V TA = -55 C, +25 C, +125 C 0 512 1024 1536 2048 2560 3072 DIGITAL INPUT CODE - Decimal 3584 4096
0.18750 0.08375 0 -0.09375 -0.18750 -0.23125 -0.37500 VREFH = +10V VREFL = 0V TA = +25 C 0 512 1024 1536 2048 2560 3072 DIGITAL INPUT CODE - Decimal 3584 4096
Figure 15. Channel-to-Channel Matching (VSUPPLY = 15 V)
1.00 0.75 VDD = +5.0V VSS = 0V VREFH = +2.5V TA = +25 C 2.0
Figure 18. INL vs. Code
1.5
LINEARITY ERROR - LSB
0.50 0.25 0 -0.25 -0.50
VDD = +15V VSS = -15V VREFH = +10V VREFL = -10V TA = +25 C
IVREFH - mA
1.0
0.5
0 -0.75 -1.00 -0.5 0 512 1024 1536 2048 2560 3072 DIGITAL INPUT CODE - Decimal 3584 4096 0 511 1023 1535 2047 2559 3071 DIGITAL INPUT CODE - Decimal 3583 4095
Figure 16. Channel-to-Channel Matching (VSUPPLY = +5 V/GND)
Figure 19. IVREFH vs. Code
13 VDD = +15V VSS = -15V VREFL = -10V
10
IDD - mA
7 4 -7
-3
1 5 VREFH - Volts
9
13
Figure 17. IDD vs. VREFH All DACs High
-8-
REV. D
DAC8412/DAC8413
32.5mV +5V INPUT 0 15.5mV 0 INPUT -5V VDD = +15V VSS = -15V VREFH = +10V VREFL = -10V TA = +25 C 1V/ DIV EA TRIG'D VDD = +15V VSS = -15V VREFH = +10V VREFL = -10V TA = +25 C 10V
5mV/DIV V 5 DIV TRIG'D
1 LSB ERROR BAND
2mV/DIV 5V DIV
VDD = +15V VSS = -15V VREFH = +10V VREFL = -10V TA = +25 C 2 s/DIV 18.04 s
TRIG'D
-17.5mV -1.96 s
-4.5mV -1.96 s
2 s/DIV
18.04 s
0V -580ns
1 s/DIV
9.42 s
Figure 20. Settling Time (Positive)
Figure 21. Settling Time (Negative)
Figure 22. Positive Slew Rate
10V
1.0 VDD = +15V VSS = -15V VREFH = +10V VREFL = -10V TA = +25 C
12 VDD = +15V VSS = -15V VREFH = +10V VREFL = -10V TA = +25 C
FULL SCALE VOLTAGE - V
0.8
10
INL - LSB
1V/ DIV EA TRIG'D
0.6
8
VDD = +15V VSS = -15V VREFH = +10V VREFL = -10V TA = +25 C
0.4
6
0.2
4
0.0 -0.2 0.01
2 0 0.01
0V -580ns
1 s/DIV
9.42 s
0.10 1.00 10.0 LOAD RESISTANCE - K
100
0.10 1.00 10.0 LOAD RESISTANCE - K
100
Figure 23. Negative Slew Rate
Figure 24. DAC 8412 INL vs. Load Resistance
10
Figure 25. DAC 8412 Output Swing vs. Load Resistance
100 POWER SUPPLY REJECTION - dB +PSRR 80 -PSRR 60 +PSRR: VDD = +15V 1Vp VSS = -15V -PSRR: VDD = +15V VSS = -15V 1V VREFH = 10V ALL DATA 0 100 1k 10k 100k FREQUENCY - Hz 1M
POWER SUPPLY CURRENT - mA
6 VDD = +15V VSS = -15V 2
IDD
0 GAIN - dB -10
-30
-50
VDD = +15V VSS = -15V VREFH = 0 100mV VREFL = -10V DATA BITS = +5V 200mV p-p
-2 ISS -6
40
20
0
10
100 1k 10k 100k FREQUENCY - Hz
1M
10M
-10 -75
0 75 TEMPERATURE - C
150
0 10
Figure 26. Small Signal Response
Figure 27. Power Supply Current vs. Temperature
Figure 28. PSRR vs. Frequency
REV. D
-9-
DAC8412/DAC8413
10.0 VDD = +15V VSS = -15V VREFH = +10V VREFL = -10V TA = +25 C
IOUT - mA
0 30 20 10 0 -10 -20 -30 -ISC VDD = +15V VSS = -15V VREFH = +10V VREFL = -10V TA = +25 C DATA = 000H +ISC
NOISE DENSITY - V
1.00
CH1 MEAN 66.19 V 1 VDD = +15V VSS = -15V VREFH = +10V VREFL = -10V TA = +25 C
0.10
0.01
20uV/DIV
M 200 s
A CH1
12.9mV
0.001 1 10 100 1000 NOISE FREQUENCY - Hz 10000
0 -25 -20 -15 -10 -5 0 5 VOUT - Volts
10
15 20
25
Figure 29. DAC8412 Noise Frequency vs. Noise Density
25 20 15 10
IOUT - mA
Figure 30. IOUT vs. VOUT
Figure 31. Broadband Noise
10 s
5 0 -5 -10 -15 -20 -25 -6
VDD = +15V VSS = 0V VREFH = +10V VREFL = 0V TA = +25 C DATA = 800H
+ISC
1V 4s GLITCH AT DAC OUTPUT
2
1
-ISC
1V
DEGLITCHER OUTPUT CH2 1.86V
-4
-2 0 2 VOUT - Volts
4
6
Figure 32. IOUT vs. VOUT
Figure 33. Glitch and Deglitched Results
OPERATION Introduction
The DAC8412 and DAC8413 are quad, voltage output, 12-bit parallel input DACs featuring a 12-bit data bus with readback capability. The only differences between the DAC8412 and DAC8413 are the reset functions. The DAC8412 resets to midscale (code 800H) and the DAC8413 resets to minimum scale (code 000H). The ability to operate from a single +5 V supply is a unique feature of these DACs. Operation of the DAC8412 and DAC8413 can be viewed by dividing the system into three separate functional groups: the digital I/O and logic, the digital to analog converters and the output amplifiers.
DACs
precision instrumentation control, a deglitcher circuit can be implemented with a standard sample-and-hold circuit. (See Figure 34.) When CS is enabled by synchronizing the hold period to be longer than the glitch tradition, the output voltage can be smoothed with minimum disturbance. A quad sampleand-hold amplifier, SMP04, has been used to illustrate the deglitching result. (See Figure 33.)
DACOUT DACOUT' S/H
DACOUT
Each DAC is a voltage switched, high impedance (R = 50 k), R-2R ladder configuration. Each 2R resistor is driven by a pair of switches that connect the resistor to either VREFH or VREFL.
Glitch
CS
S/H
H
S
H
S
Worst-case glitch occurs at the transition between half-scale digital code 1000 0000 0000 to half-scale minus 1 LSB, 0111 1111 1111. It can be measured at about 2 V s. (See Figure 33.) For demanding applications such as waveform generation or
DACOUT'
Figure 34. Deglitcher Circuit
-10-
REV. D
DAC8412/DAC8413
Reference Inputs
All four DACs share common reference high (VREFH) and reference low (VREFL) inputs. The voltages applied to these reference inputs set the output high and low voltage limits of all four of the DACs. Each reference input has voltage restrictions with respect to the other reference and to the power supplies. The VREFL can be set at any voltage between VSS and VREFH - 2.5 V, and VREFH can be set to any value between +VDD - 2.5 V and VREFL + 2.5 V. Note that because of these restrictions the DAC8412 references cannot be inverted (i.e., VREFL cannot be greater than VREFH). It is important to note that the DAC8412's VREFH input both sinks and sources current. Also the input current of both VREFH and VREFL are code dependent. Many references have limited current sinking capability and must be buffered with an amplifier to drive VREFH. The VREFL has no such special requirements. It is recommended that the reference inputs be bypassed with 0.2 F capacitors when operating with 10 V references. This limits the reference bandwidth.
Digital I/O
The R/W input, when enabled by CS, controls the writing to and reading from the input register.
Coding
Both the DAC8412 and DAC8413 use binary coding. The output voltage can be calculated by:
VOUT = VREFL + (VREF H _ VREFL ) x N 4096
where N is the digital code in decimal.
RESET
The RESET function can be used either at power-up or at any time during the DAC's operation. The RESET function is independent of CS. This pin is active LOW and sets the DAC output registers to either center code for the DAC8412, or zero code for the DAC8413. The reset to center code is most useful when the DAC is configured for bipolar references and an output of zero volts after reset is desired.
Supplies
See Table I for digital control logic truth table. Digital I/O consists of a 12-bit bidirectional data bus, two registers select inputs, A0 and A1, a R/W input, a RESET input, a Chip Select (CS), and a Load DAC (LDAC) input. Control of the DACs and bus direction is determined by these inputs as shown in Table I. Digital data bits are labeled with the MSB defined as data bit "11" and the LSB as data bit "0." All digital pins are TTL/ CMOS compatible. See Figure 35 for a simplified I/O logic diagram. The register select inputs A0 and A1 select individual DAC registers "A" (binary code 00) through "D" (binary code 11). Decoding of the registers is enabled by the CS input. When CS is high no decoding takes place, and neither the writing nor the reading of the input registers is enabled. The loading of the second bank of registers is controlled by the asynchronous LDAC input. By taking LDAC low while CS is enabled, all output registers can be updated simultaneously. Note that the tLDW required pulsewidth for updating all DACs is a minimum of 170 ns.
Supplies required are VSS, VDD and VLOGIC. The VSS supply can be set between -15 V and 0 V. VDD is the positive supply; its operating range is between +5 V and +15 V. VLOGIC is the digital output supply voltage for the readback function. It is normally connected to +5 V. This pin is a logic reference input only. It does not supply current to the device. If you are not using the readback function, VLOGIC can be left opencircuit. While VLOGIC does not supply current to the DAC8412, it does supply currents to the digital outputs when readback is used.
Amplifiers
Unlike many voltage output DACs, the DAC8412 features buffered voltage outputs. Each output is capable of both sourcing and sinking 5 mA at 10 volts, eliminating the need for external amplifiers when driving 500 pF or smaller capacitive load in most applications. These amplifiers are short-circuit protected.
Table I. DAC8412/DAC8413 Logic Table
A1 L L H H L L H H L L H H X X X X
A0 L H L H L H L H L H L H X X X X
R/W L L L L L L L L H H H H X X X X
CS L L L L L L L L L L L L H H X H
RS H H H H H H H H H H H H H H L g
LDAC L L L L H H H H H H H H L H X X
INPUT REG
OUTPUT REG
MODE
DAC A B C D A B C D A B C D All All All All
WRITE WRITE Transparent WRITE WRITE Transparent WRITE WRITE Transparent WRITE WRITE Transparent WRITE HOLD WRITE INPUT WRITE HOLD WRITE INPUT WRITE HOLD WRITE INPUT WRITE HOLD WRITE INPUT READ HOLD READ INPUT READ HOLD READ INPUT READ HOLD READ INPUT READ HOLD READ INPUT HOLD Update all output registers HOLD HOLD HOLD *All registers reset to mid/zero-scale *All registers latched to mid/zero-scale
*DAC8412 resets to midscale, and DAC8413 resets to zero scale. L = Logic Low; H = Logic High; X - Don't Care. Input and Output registers are transparent when asserted.
REV. D
-11-
DAC8412/DAC8413
VREFH RDDACA WRDB0 WRDB1 WRDACA WRDB2 WRDB3 WRDB4 WRDACB INPUT REGISTER WRDB6 RDDACC WRDB7 WRDACC WRDB8 WRDB9 RDDACD WRDB10 WRDB11 WRDACD DB11..DB0 VLOGIC DAC D VOUTD OUTPUT WRDB5 REGISTER DAC B VOUTB DAC A VOUTA VDD VSS CS
A0
RDDACB
A1
DAC C VOUTC
R/W
VREFL LDAC RESET READOUTBAR READBACKDATAIN_DB11 READBACK DATAOUT_DB11 READOUT READBACKDATAIN_DB10
DGND
Figure 35. Simplified I/O Logic Diagram
Careful attention to grounding is important to accurate operation of the DAC8412. This is not because the DAC8412 is more sensitive than other 12-bit DACs, but because with four outputs and two references there is greater potential for ground loops. Since the DAC8412 has no analog ground, the ground must be specified with respect to the reference.
Reference Configurations
+15V 39k +15V
6.2 BALANCE 100k 0.2 F
VDD VREFH
Output voltage ranges can be configured as either unipolar or bipolar, and within these choices a wide variety of options exists. The unipolar configuration can be either positive or negative voltage output, and the bipolar configuration can be either symmetrical or nonsymmetrical.
+15V +15V + INPUT OUTPUT OP-400 OP400 VREFH 0.2 F VDD
GAIN 100k
AD688 FOR 10V AD588 FOR 5V
6.2
DAC8412 OR DAC8413
VREFL 0.2 F VSS
0.1 F //10 F
1F 5 OR -15V 10V OPERATION
Figure 37. Symmetrical Bipolar Operation
0.1 F //10 F
REF10
TRIM 10k VREFL +10V OPERATION
DAC8412 OR DAC8413
VSS
-15V
Figure 36. Unipolar +10 V Operation
Figure 37 (Symmetrical Bipolar Operation) shows the DAC8412 configured for 10 V operation. Note: See the AD688 data sheet for a full explanation of reference operation. Adjustments may not be required for many applications since the AD688 is a very high accuracy reference. However if additional adjustments are required, adjust the DAC8412 full scale first. Begin by loading the digital full-scale code (FFFH), and then adjust the Gain Adjust potentiometer to attain a DAC output voltage of 9.9976 V. Then, adjust the Balance Adjust to set the center scale output voltage to 0.000 V.
-12-
REV. D
DAC8412/DAC8413
The 0.2 F bypass capacitors shown at the reference inputs in Figure 37 should be used whenever 10 V references are used. Applications with single references or references to 5 V may not require the 0.2 F bypassing. The 6.2 resistor in series with the output of the reference amplifier is to keep the amplifier from oscillating with the capacitive load. We have found that this is large enough to stabilize this circuit. Larger resistor values are acceptable, provided that the drop across the resistor doesn't exceed a VBE. Assuming a minimum VBE of 0.6 V and a maximum current of 2.75 mA, then the resistor should be under 200 for the loading of a single DAC8412. Using two separate references is not recommended. Having two references could cause different drifts with time and temperature; whereas with a single reference, most drifts will track. Unipolar positive full-scale operation can usually be set with a reference with the correct output voltage. This is preferable to using a reference and dividing down to the required value. For a 10 V full-scale output, the circuit can be configured as shown in Figure 38. In this configuration the full-scale value is set first by adjusting the 10 k resistor for a full-scale output of 9.9976 V.
10k VSS TRIM VREFH OUTPUT 0.2 F 0.01 F 10 F ZERO TO -10V OPERATION -15V VREFL VSS VDD ZERO TO +2.5V OPERATION SINGLE +5V SUPPLY 0.1 F //10 F
Figure 38 shows the DAC8412 configured for -10 V to 0 V operation. A REF08 with a -10 V output is connected directly to VREFL for the reference voltage.
Single +5 V Supply Operation
For operation with a +5 V supply, the reference voltage should be set between 1.0 V and +2.5 V for optimum linearity. Figure 39 shows a REF43 used to supply a +2.5 V reference voltage. The headroom of the reference and DAC are both sufficient to support a +5 V supply with 5% tolerance. VDD and VLOGIC should be connected to the same supply. Separate bypassing to each pin should also be used.
+5V 10 F INPUT OUTPUT VREFH 0.2 F 10k GND VREFL 0.01 F
VDD
REF43
TRIM
DAC8412 OR DAC8413
0.1 F //10 F
GND
REF08
DAC8412 OR DAC8413
Figure 39. +5 V Single Supply Operation
Figure 38. Unipolar -10 V Operation
REV. D
-13-
DAC8412/DAC8413
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Position Leadless Chip Carrier (TC Suffix)
0.075 (1.91) REF 0.095 (2.41) 0.075 (1.90) TOP VIEW 0.458 (11.63) MAX SQ 0.011 (0.28) 0.007 (0.18) R TYP 0.075 (1.91) REF 0.088 (2.24) 0.054 (1.37)
19 18 26 25 28 1 5
0.458 (11.63) 0.442 (11.23) SQ
0.100 (2.54) 0.064 (1.63)
0.300 (7.62) BSC 0.150 (3.51) BSC
4
0.015 (0.38) MIN 0.028 (0.71) 0.022 (0.56) 0.050 (1.27) BSC
11 12
BOTTOM VIEW
0.055 (1.40) 0.045 (1.14)
0.200 (5.08) BSC
45 TYP
28-Lead PLCC (P-28A) (PC Suffix)
0.048 (1.21) 0.042 (1.07) 0.048 (1.21) 0.042 (1.07)
4 5 PIN 1 IDENTIFIER
0.180 (4.57) 0.165 (4.19) 0.056 (1.42) 0.042 (1.07)
26 25
0.025 (0.63) 0.015 (0.38) 0.021 (0.53) 0.013 (0.33)
TOP VIEW
(PINS DOWN) 11 12 19 18
0.050 (1.27) BSC
0.032 (0.81) 0.026 (0.66)
0.430 (10.92) 0.390 (9.91)
0.020 (0.50) R
0.456 (11.58) SQ 0.450 (11.43) 0.495 (12.57) SQ 0.485 (12.32)
0.040 (1.01) 0.025 (0.64) 0.110 (2.79) 0.085 (2.16)
28-Lead Epoxy DIP (N-28) (P Suffix)
1.565 (39.70) 1.380 (35.10)
28 15
0.580 (14.73) 0.485 (12.32)
1 14
0.060 (1.52) 0.015 (0.38)
0.625 (15.87) 0.600 (15.24) 0.195 (4.95) 0.125 (3.18)
0.250 (6.35) MAX 0.200 (5.05) 0.022 (0.558) 0.125 (3.18) 0.014 (0.356)
0.150 (3.81) MIN 0.100 (2.54) BSC 0.070 SEATING (1.77) PLANE MAX
0.015 (0.381) 0.008 (0.204)
-14-
REV. D
PRINTED IN U.S.A.
PIN 1
C1544a-2-3/00 (rev. D)
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